IDiyas

For the Inventor, By the Inventor

Tokyo, Japan

Toshiki Kanamoto

USPTO Granted Patents = 9

Average Co-Inventor Count = 2.5

ph-index = 4

Forward Citations = 141(Granted Patents)


Location History:

  • Tokyo, JP (2002 - 2011)
  • Kanagawa, JP (2016)

Company Filing History:

goldMedal3 out of 21,351 
 
Mitsubishi Denki Kabushiki Kaisha
 patents
silverMedal3 out of 3,781 
 
Renesas Technology Corp.
 patents
bronzeMedal2 out of 27,375 
 
Matsushita Electric Industrial Co., Ltd.
 patents
4. 2 out of 7,524 
 
Renesas Electronics Corporation
 patents
where one patent can have more than one assignee

Years Active: 2002-2016

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9 patents (USPTO):Explore Patents
1. 9405873 - Method for improved accuracy of a substrate parasitic-resistance extraction in a circuit simulation (2016-08-02),
2. 7979817 - Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing (2011-07-12),
3. 7432581 - Semiconductor device, method of manufacture thereof and semiconductor integrated circuit (2008-10-07),
4. 7398506 - Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing (2008-07-08),
5. 7230435 - Capacitance measurement circuit (2007-06-12),
6. 6982555 - Semiconductor device (2006-01-03),
7. 6728943 - Semiconductor circuit extraction apparatus and method (2004-04-27),
8. 6504186 - Semiconductor device having a library of standard cells and method of designing the same (2003-01-07),
9. 6442740 - Clock signal analysis device and clock signal analysis method (2002-08-27),
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