Tokyo, Japan

Toshiki Kanamoto

This inventor holds 9 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.. Active years: 2002-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Toshiki Kanamoto. Retrieved from https://idiyas.com/inventor/toshiki-kanamoto

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 33.3

Average Co-Inventor Count = 2.5

ph-index = 4

Forward Citations = 141(Granted Patents)


Location History:

  • Tokyo, JP (2002 - 2011)
  • Kanagawa, JP (2016)

Company Filing History:


Years Active: 2002-2016

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9 patents (USPTO):Explore Patents

Title: Innovations of Toshiki Kanamoto

Introduction

Toshiki Kanamoto is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 9 patents. His work focuses on improving the accuracy of circuit simulations and enhancing the performance of memory cells.

Latest Patents

One of his latest patents is a method for improved accuracy of a substrate parasitic-resistance extraction in a circuit simulation. This innovation considers a Deep Nwell diffusing into a Pwell region, which enhances the accuracy of the extraction process. By dividing the well region of a semiconductor integrated circuit into multiple meshes, each containing resistor segments, he analyzes substrate noise effectively. The method involves deleting parallel components of resistors that couple the Pwell with the substrate, reflecting the rise in resistance value caused by the Deep Nwell. This approach significantly improves the accuracy of substrate parasitic-resistance extraction.

Another notable patent is a net list producing device that generates a net list with an interconnection parasitic element through hierarchical processing. This device utilizes a memory cell information producing unit to obtain essential data such as physical terminal coordinates and names. It specifies parasitic elements on interconnections of the memory cell and produces comprehensive memory cell information. The memory cell array information producing unit further enhances this by determining the connection relationships of physical terminals and producing a net list of the memory cell array.

Career Highlights

Toshiki Kanamoto has worked with several esteemed companies, including Mitsubishi Electric Corporation and Renesas Technology Corporation. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking innovations in semiconductor technology.

Collaborations

Throughout his career, Kanamoto has collaborated with notable professionals in the field, including Tetsuya Watanabe and Tatsuya Kunikiyo. These collaborations have fostered an environment of innovation and have led to the development of advanced technologies.

Conclusion

Toshiki Kanamoto's contributions to semiconductor technology through his patents and collaborations highlight his role as a significant inventor in the industry. His innovative methods continue to influence the accuracy and efficiency of circuit simulations and memory cell designs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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