The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9405873 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 02, 2016

Filed:

Dec. 03, 2012
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Toshiki Kanamoto, Kanagawa, JP;

Hisato Inaba, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01);
Abstract

By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved.


Find Patent Forward Citations

Kanamoto, Toshiki. (2016). Method for improved accuracy of a substrate parasitic-resistance extraction in a circuit simulation (U.S. Patent No. 9405873). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9405873

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