The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2007
Filed:
Jan. 21, 2004
Tatsuya Kunikiyo, Tokyo, JP;
Tetsuya Watanabe, Tokyo, JP;
Toshiki Kanamoto, Tokyo, JP;
Kyoji Yamashita, Kyoto, JP;
Tatsuya Kunikiyo, Tokyo, JP;
Tetsuya Watanabe, Tokyo, JP;
Toshiki Kanamoto, Tokyo, JP;
Kyoji Yamashita, Kyoto, JP;
Renesas Technology Corp., Tokyo, JP;
Matsushita Electric Industrial Co., Ltd., Kadoma-shi, JP;
Abstract
A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N) is electrically connected to a terminal (P) between the drains of PMOS and NMOS transistors (MP, MN). As a target capacitance forming part, a coupling capacitance (C) is formed between the node (N) and a node (N). The node (N) is connected to a pad () through the terminal (P) and an NMOS transistor (MN), and a node (N) is connected to a terminal (P) between the drains of PMOS and NMOS transistors (MP, MN). A reference capacitance (C) is formed at the node (N) as a dummy capacitance. Currents (I, I) supplied from a power source to the nodes (N, N) are measured with current meters (), respectively and a current (I) induced from the node (N) and flowing to a ground level is measured with a current meter ().