Clock signal analysis device and clock signal analysis method

Abstract

A clock signal analysis device ( ) has a pre-processing section ( ) for reading circuit connection information, transistor characteristic information, and control information stored in memories ( ) and for editing those information to be used for a simulation by a simulation execution section ( ). The simulation execution section ( ) executes a simulation of circuit operation, and then an after-processing section ( ) calculates a delay value from a clock signal input node to a clock signal terminal node, a difference between delay values of clock signal terminal nodes, a rising time, a falling time of the clock signal and displays an analysis result by using a two-dimensional distribution map through a monitor ( ).