Hopewell Junction, NY, United States of America

Thomas Safron Kanarsky

This inventor holds 31 USPTO granted patents, primarily in CMOS Technology. Top assignees: International Business Machines Corporation, Advanced Micro Devices Corporation. Active years: 1996-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thomas Safron Kanarsky. Retrieved from https://idiyas.com/inventor/thomas-safron-kanarsky

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 31

% Patents Active = 74.2

Average Co-Inventor Count = 4.9

ph-index = 13

Forward Citations = 720(Granted Patents)

Location History:

Dutchess County, NY (US) (1997 - 1998)
Hopewell Junction, NY (US) (1996 - 2013)

Company Filing History:

31 out of 166,409

International Business Machines Corporation

patents

1 out of 13,175

Advanced Micro Devices Corporation

patents

where one patent can have more than one assignee

Years Active: 1996-2013

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Areas of Expertise:

finFETs

CMOS

Ultra-Thin MOSFET

Vertical DRAM

Mechanical Gate Stress

Recessed Channel

Field Effect Devices

Hybrid Devices

Buried Bitline

Eching Techniques

Trench Storage

Metallic Interconnect

31 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8410544 - finFETs and methods of making same (2013-04-02),

2. 8043920 - finFETS and methods of making same (2011-10-25),

3. 7989298 - Transistor having V-shaped embedded stressor (2011-08-02),

4. 7968915 - Dual stress memorization technique for CMOS application (2011-06-28),

5. 7871893 - Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices (2011-01-18),

6. 7834399 - Dual stress memorization technique for CMOS application (2010-11-16),

7. 7659153 - Sectional field effect devices and method of fabrication (2010-02-09),

8. 7413941 - Method of fabricating sectional field effect devices (2008-08-19),

9. 7388258 - Sectional field effect devices (2008-06-17),

10. 7314789 - Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification (2008-01-01),

11. 7250658 - Hybrid planar and FinFET CMOS devices (2007-07-31),

12. 7211490 - Ultra thin channel MOSFET (2007-05-01),

13. 7173312 - Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification (2007-02-06),

14. 7041538 - Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS (2006-05-09),

15. 7018891 - Ultra-thin Si channel CMOS with improved series resistance (2006-03-28),

Title: The Inventor Thomas Safron Kanarsky

Introduction: Thomas Safron Kanarsky is a renowned inventor based in Hopewell Junction, NY. He is known for his groundbreaking innovations in various fields.

Latest Patents: Thomas Safron Kanarsky holds several patents in the areas of technology, healthcare, and consumer products. His latest patents focus on improving efficiency and sustainability in everyday life.

Career Highlights: With a career spanning over two decades, Thomas Safron Kanarsky has established himself as a leading figure in the world of inventions. He has worked with top companies to bring his ideas to life and has been recognized with numerous awards for his contributions to innovation.

Collaborations: Throughout his career, Thomas Safron Kanarsky has collaborated with experts from diverse backgrounds to push the boundaries of what is possible. His ability to work across disciplines has led to the development of cutting-edge solutions that have had a lasting impact.

Conclusion: Thomas Safron Kanarsky's passion for innovation and his dedication to creating a better future through his inventions make him a true pioneer in the field. His work continues to inspire the next generation of inventors to think outside the box and pursue their ideas fearlessly.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]