The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7211490 B1

PDF
Full Text
Expired
Date of Patent:
May. 01, 2007

Filed:

Mar. 18, 2005
Applicants:

Bruce B. Doris, Brewster, NY (US);

Thomas S. Kanarsky, Hopewell Junction, NY (US);

Ying Zhang, Yorktown Heights, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Meikei Ieong, Wappingers Falls, NY (US);

Omer Dokumaci, Wappingers Falls, NY (US);

Inventors:

Bruce B. Doris, Brewster, NY (US);

Thomas S. Kanarsky, Hopewell Junction, NY (US);

Ying Zhang, Yorktown Heights, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Meikei Ieong, Wappingers Falls, NY (US);

Omer Dokumaci, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.


Find Patent Forward Citations

Doris, Bruce. (2007). Ultra thin channel mosfet (U.S. Patent No. 7211490). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7211490

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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