The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2007
Filed:
Dec. 15, 2004
Cyril Cabral, Jr., Mahopac, NY (US);
Bruce B. Doris, Hopewell Junction, NY (US);
Thomas S. Kanarsky, Hopewell Junction, NY (US);
Xiao H. Liu, Croton-on-Hudson, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Cyril Cabral, Jr., Mahopac, NY (US);
Bruce B. Doris, Hopewell Junction, NY (US);
Thomas S. Kanarsky, Hopewell Junction, NY (US);
Xiao H. Liu, Croton-on-Hudson, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.