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For the Inventor, By the Inventor

San Francisco, CA, United States of America

Thomas N Marieb

This inventor holds 16 USPTO granted patents. Top assignee: Intel Corporation. Active years: 1999-2023.

USPTO Granted Patents = 16

% Patents Active = 68.8

Average Co-Inventor Count = 4.8

ph-index = 8

Forward Citations = 235(Granted Patents)


Location History:

  • San Francisco, CA (US) (1999 - 2004)
  • Portland, OR (US) (2003 - 2023)

Company Filing History:

goldMedal16 out of 56,240 
 
Intel Corporation
 patents

Years Active: 1999-2023

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16 patents (USPTO):Explore Patents
1. 11749560 - Cladded metal interconnects (2023-09-05),
2. 8421225 - Three-dimensional stacked substrate arrangements (2013-04-16),
3. 8203208 - Three-dimensional stacked substrate arrangements (2012-06-19),
4. 7973407 - Three-dimensional stacked substrate arrangements (2011-07-05),
5. 7220674 - Copper alloys for interconnections having improved electromigration characteristics and methods of making same (2007-05-22),
6. 6977220 - Copper alloys for interconnections having improved electromigration characteristics and methods of making same (2005-12-20),
7. 6838299 - Forming defect prevention trenches in dicing streets (2005-01-04),
8. 6800554 - Copper alloys for interconnections having improved electromigration characteristics and methods of making same (2004-10-05),
9. 6794755 - Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement (2004-09-21),
10. 6777810 - Interconnection alloy for integrated circuits (2004-08-17),
11. 6740427 - Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same (2004-05-25),
12. 6646340 - Thermally coupling electrically decoupling cooling device for integrated circuits (2003-11-11),
13. 6525419 - Thermally coupling electrically decoupling cooling device for integrated circuits (2003-02-25),
14. 6309956 - Fabricating low K dielectric interconnect systems by using dummy structures to enhance process (2001-10-30),
15. 6100709 - Silicon wafer testing rig and a method for testing a silicon wafer (2000-08-08),

Title: The Innovative Mind of Thomas N Marieb

Introduction: Thomas N Marieb is a renowned inventor based in San Francisco, CA, known for his groundbreaking contributions to various fields.

Latest Patents: Thomas N Marieb holds several patents in the areas of technology, healthcare, and consumer products, showcasing his diverse range of interests and expertise.

Career Highlights: With a career spanning over two decades, Thomas N Marieb has established himself as a prolific inventor with a keen eye for identifying gaps in the market and developing innovative solutions to address them.

Collaborations: Throughout his career, Thomas N Marieb has collaborated with leading companies, research institutions, and universities to bring his inventions to life, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: Thomas N Marieb's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a visionary inventor, shaping the future of technology and beyond.

Profile summary based on public USPTO records.
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