The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2004

Filed:

Dec. 18, 2000
Applicant:
Inventors:

Thomas N. Marieb, Portland, OR (US);

Paul McGregor, Hillsboro, OR (US);

Carolyn Block, Portland, OR (US);

Shu Jin, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines. In this way, electromigration resistance and adhesion characteristics may be improved by having relatively higher doping concentrations at outer portions of an interconnect line while the desired low electrical resistivity of the interconnect is maintained by keeping the interior portions of the interconnect with a substantially lower doping concentration.


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