Intel Corporation

Thomas N Marieb

Paul McGregor

Carolyn Block

Patrick R Morrow

Kevin O'Brien

Mauro J Kobrinsky

Sarah E Kim

Shriram Ramanathan

Michael Y Chan

Michael C Harmes

Shu Jin

Scott List

Donald S Gardner

Daniel Pantuso

Zhiyong Ma

Timothy L Deeter

Sarangapani Sista

Daniel Murray

Christopher J Jezewski

Krishna Seshan

Subhash M Joshi

Chien Chiang

David B Fraser

Jin Hyung Lee

Quat T Vu

Miriam Ruth Reshotko

Steven N Towle

Jihperng Leu

Markus Kuhn

Jun He

Jose A Maiz

Mitchell C Taylor

Chuanbin Pan

Simon Yang

Madhav Datta

Flavio Griggio

Xiaorong Morrow

Sychyi Fang

Dave Emory

Susanne Menezes

Doowon Suh

Rose Mulligan

Vicky M Ochoa

Tzeun-luh Huang

Donald L Scharfetter

Rahim Kasim

Sing-Mo Tzeng

Christine A King

Michael Mckeag

Anne S Mack

Nikholas G Toledo

Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

Cladded metal interconnects

Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Three-dimensional stacked substrate arrangements

Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines. In this way, electromigration resistance and adhesion characteristics may be improved by having relatively higher doping concentrations at outer portions of an interconnect line while the desired low electrical resistivity of the interconnect is maintained by keeping the interior portions of the interconnect with a substantially lower doping concentration.

Copper alloys for interconnections having improved electromigration characteristics and methods of making same

A method of dicing a microelectronic device wafer comprising forming at least one trench in at least one dicing street on the microelectronic device wafer, wherein the trench prevents cracking and/or delamination problems in the interconnect layer of the microelectronic device wafers caused by a subsequent dicing by a wafer saw.

Forming defect prevention trenches in dicing streets

Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.

Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement

An interconnection of an aluminum-copper-titanium alloy containing about 0.1 atomic percent titanium.

Interconnection alloy for integrated circuits

The invention relates to a ball limiting metallurgy stack for an electrical device that contains a tin diffusion barrier and thermo-mechanical buffer layer disposed upon a refractory metal first layer. The multi-diffusion barrier layer stack resists tin migration toward the upper metallization of the device.

Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same

A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.

Thermally coupling electrically decoupling cooling device for integrated circuits

The present invention relates to semiconductor devices. More specifically, the invention discloses the use of dummy structures to improve thermal conductivity, reduce dishing and strengthen layers formed with low dielectric constant materials.

Fabricating low K dielectric interconnect systems by using dummy structures to enhance process

A wafer testing rig includes a stand, a first contact component, a second contact component and a biasing device. The first contact component is mounted to the stand. The second contact component is mounted to the stand for movement towards and away from the first contact component. The first and second contact components are shaped so that a wafer, when located between the contact components, is deflected into a dome shape when the second contact component is moved towards the first contact component. The biasing device is operable to move the second contact component towards and away from the first contact component. An electrical tester is provided to test the wafer.

Silicon wafer testing rig and a method for testing a silicon wafer

Growing community of inventors

San Francisco, CA, United States of America

Thomas N Marieb