Voreppe, France

Thierry Poiroux

USPTO Granted Patents = 21 

 

Average Co-Inventor Count = 3.3

ph-index = 4

Forward Citations = 65(Granted Patents)


Location History:

  • Voreppe, FR (2004 - 2013)
  • Voiron, FR (2013 - 2021)

Company Filing History:


Years Active: 2004-2021

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21 patents (USPTO):Explore Patents

Title: Innovations and Contributions of Thierry Poiroux in Nanotechnology

Introduction: Thierry Poiroux, based in Voreppe, France, is an accomplished inventor with a remarkable portfolio of 21 patents. His work primarily focuses on advancements in nanotechnology, particularly in the field of transistors.

Latest Patents: Among Thierry Poiroux's latest innovations is a computer-implemented method for determining intrinsic parameters in stacked nanowires MOSFETs. This invention addresses the need for accuracy in the intrinsic parameters of stacked nanowires and nanosheets in Gate-All-Around (GAA) MOSFETs. Additionally, he has developed a computer-implemented method for calculating charge density at a gate interface of a double gate transistor. This method enhances the precision of charge density calculations essential for improved performance of thin body double gate transistors.

Career Highlights: Thierry Poiroux has made significant contributions during his tenure at prestigious organizations, including the Commissariat à l'Énergie Atomique and the Commissariat à l'Énergie Atomique et aux Énergies Alternatives. His expertise in semiconductor technologies and innovative approaches have been pivotal to his success as an inventor.

Collaborations: Throughout his career, Thierry has collaborated with notable colleagues such as Maud Vinet and Olivier Rozeau. These partnerships have helped foster a collaborative environment that encourages innovative ideas and advancements.

Conclusion: Thierry Poiroux exemplifies the spirit of innovation in nanotechnology through his extensive patent portfolio and collaborative efforts. His contributions are vital for the ongoing advancements in the field, paving the way for improved technologies in transistor design and functionality.

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