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Voreppe, France

Thierry Poiroux

This inventor holds 21 USPTO granted patents and 1 published patent application and 11 EPO patents, primarily in Transistor Technology. Top assignees: Commissariat a L'energie Atomique Et Aux Energies Alternatives, STMicroelectronics, Stmicroelectronics (Grenoble 2) Sas. Active years: 2004-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thierry Poiroux. Retrieved from https://idiyas.com/inventor/thierry-poiroux

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 52.4

 

Average Co-Inventor Count = 3.3

ph-index = 4

Forward Citations = 67(Granted Patents)


Location History:

  • Voreppe, FR (2004 - 2013)
  • Voiron, FR (2013 - 2021)

Company Filing History:

goldMedal19 out of 8,833 
 
Commissariat a L'energie Atomique Et Aux Energies Alternatives
 patents
silverMedal1 out of 2,426 
 
STMicroelectronics
 patents
bronzeMedal1 out of 647 
 
Stmicroelectronics (Grenoble 2) Sas
 patents
4. 2 out of 834,570 
Other
 patents
where one patent can have more than one assignee

Years Active: 2004-2021

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Areas of Expertise:
MOSFET
Double-Gate Transistor
Integrated Circuit
Strained Channel
Charge Density
Electromechanical Component
Graphene
CMOS Cell
Germanium-Based Channel
Transistor Fabrication
Silicidation
Piezoelectric Layer
21 patents (USPTO):Explore Patents
1. 10914703 - Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET (2021-02-09),
2. 9235668 - Computer implemented method for calculating a charge density at a gate interface of a double gate transistor (2016-01-12),
3. 9093552 - Manufacturing method for a device with transistors strained by silicidation of source and drain zones (2015-07-28),
4. 8877622 - Process for producing an integrated circuit (2014-11-04),
5. 8866225 - Field effect transistor with alternate electrical contacts (2014-10-21),
6. 8664104 - Method of producing a device with transistors strained by means of an external layer (2014-03-04),
7. 8656584 - Method of fabricating an electromechanical component using graphene (2014-02-25),
8. 8598038 - Process for producing two interleaved patterns on a substrate (2013-12-03),
9. 8530292 - Method for manufacturing a strained channel MOS transistor (2013-09-10),
10. 8399316 - Method for making asymmetric double-gate transistors (2013-03-19),
11. 8349667 - Method for stabilizing germanium nanowires obtained by condensation (2013-01-08),
12. 8324057 - Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate (2012-12-04),
13. 8232168 - Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate (2012-07-31),
14. 8105906 - Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate (2012-01-31),
15. 8021986 - Method for producing a transistor with metallic source and drain (2011-09-20),

Title: Innovations and Contributions of Thierry Poiroux in Nanotechnology

Introduction: Thierry Poiroux, based in Voreppe, France, is an accomplished inventor with a remarkable portfolio of 21 patents. His work primarily focuses on advancements in nanotechnology, particularly in the field of transistors.

Latest Patents: Among Thierry Poiroux's latest innovations is a computer-implemented method for determining intrinsic parameters in stacked nanowires MOSFETs. This invention addresses the need for accuracy in the intrinsic parameters of stacked nanowires and nanosheets in Gate-All-Around (GAA) MOSFETs. Additionally, he has developed a computer-implemented method for calculating charge density at a gate interface of a double gate transistor. This method enhances the precision of charge density calculations essential for improved performance of thin body double gate transistors.

Career Highlights: Thierry Poiroux has made significant contributions during his tenure at prestigious organizations, including the Commissariat à l'Énergie Atomique and the Commissariat à l'Énergie Atomique et aux Énergies Alternatives. His expertise in semiconductor technologies and innovative approaches have been pivotal to his success as an inventor.

Collaborations: Throughout his career, Thierry has collaborated with notable colleagues such as Maud Vinet and Olivier Rozeau. These partnerships have helped foster a collaborative environment that encourages innovative ideas and advancements.

Conclusion: Thierry Poiroux exemplifies the spirit of innovation in nanotechnology through his extensive patent portfolio and collaborative efforts. His contributions are vital for the ongoing advancements in the field, paving the way for improved technologies in transistor design and functionality.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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