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Stmicroelectronics S.a.

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (rousset) Sas

Thierry Poiroux

Maud Vinet

Olivier Rozeau

Yves Morand

Bernard Previtali

Olivier Thomas

Fabrice Nemouchi

Jean-Charles Barbe

Marie-Anne Jaud

Patrice Gergaud

Laurent Clavelier

Thomas Ernst

Philippe Andreucci

Jean-Francois Damlencourt

Jean-Christophe Gabriel

Sébastien Barnola

Joris Lacord

Gerard Billiot

Emeline Saracco

Jean-François Damlencourt

Sébastien Martinie

Sebastien Martinie

Jerome Lolivier

Phillipe Flatresse

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nnanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:

Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET

A computer implemented method for calculating a charge density qof a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate qof the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function f(q) able to be nullified by a correct value of the charge density qof the first gate.

Computer implemented method for calculating a charge density at a gate interface of a double gate transistor

A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.

Manufacturing method for a device with transistors strained by silicidation of source and drain zones

A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

Process for producing an integrated circuit

A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.

Field effect transistor with alternate electrical contacts

A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Method of producing a device with transistors strained by means of an external layer

Method of fabricating an electro-mechanical microsystem provided with at least one fixed part comprising a bar, and at least one mobile part in rotation around at least one portion of said bar, the method comprising the steps of:

Method of fabricating an electromechanical component using graphene

A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

Process for producing two interleaved patterns on a substrate

A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Method for manufacturing a strained channel MOS transistor

A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

Method for making asymmetric double-gate transistors

The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.

Method for stabilizing germanium nanowires obtained by condensation

A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.

Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate

A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate

A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.

Growing community of inventors

Voreppe, France

Thierry Poiroux