Nagano, Japan

Tatsuhiko Fujihira

This inventor holds 95 USPTO granted patents and 4 published patent applications and 3 EPO patents, primarily in Semiconductor Devices (CPC class H01L2-976). Top assignees: Fuji Electric Co., Ltd., Fuji Electric Device Technology Co., Ltd., Fuji Electric Holdings Co., Ltd.. Active years: 1991-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tatsuhiko Fujihira. Retrieved from https://idiyas.com/inventor/tatsuhiko-fujihira

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 95 

% Patents Active = 95.8

 

Average Co-Inventor Count = 2.0

ph-index = 26

Forward Citations = 2,249(Granted Patents)

Forward Citations (Not Self Cited) = 2,211(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Kanagawa, JP (1991 - 1999)
  • Kawasaki, JP (1992 - 2004)
  • Nagano, JP (1995 - 2009)
  • Matsumoto, JP (1991 - 2015)

Company Filing History:


Years Active: 1991-2015

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Areas of Expertise:
Super-Junction
Semiconductor Device
Schottky Barrier Diode
High Power
Lateral MOSFET
Electro-Static Discharge
Vertical Drain Drift Layer
Alternating Conductivity
Junction Terminating Structure
MIS Semiconductor
Combined IC
High Breakdown Voltage
95 patents (USPTO):Explore Patents

Title: Tatsuhiko Fujihira: A Pioneer in Semiconductor Innovations

Introduction

Tatsuhiko Fujihira, based in Nagano, Japan, is a prominent inventor known for his significant contributions to the field of semiconductor technology. With an impressive portfolio of 95 patents, Fujihira has made remarkable advancements that enhance the performance and efficiency of semiconductor devices.

Latest Patents

Fujihira's latest patents include innovative methods such as:

1. **Method of manufacturing a super-junction semiconductor device** - This patent reveals a technique that allows for the precise formation of a high concentration layer, improving the trade-off relationship between the Eoff and the dV/dt. The process involves creating a parallel pn layer, followed by the formation of a proton irradiated layer in the upper region of the pn layer. Subsequent heat treatment transforms the protons into donors, resulting in a high concentration n-type semiconductor layer.

2. **Semiconductor device and method of manufacturing the same** - This invention presents a cost-effective semiconductor device and manufacturing method that enhances the trade-off relationship between the Eoff and the turning OFF dV/dt using a trench embedding method. It includes steps for constructing a parallel pn layer in a superjunction structure and ion implantation into the n-type semiconductor layer to create a high concentration region, thus reducing both processing time and costs compared to conventional methods.

Career Highlights

Fujihira has held positions at renowned companies including Fuji Electric Co., Ltd. and Fuji Electric Device Technology Co., Ltd. His work at these institutions has facilitated the application of his inventive methods in real-world semiconductor manufacturing, contributing significantly to advancements in the industry.

Collaborations

Throughout his career, Fujihira has collaborated with esteemed colleagues such as Susumu Iwamoto and Yasuhiko Onishi. These partnerships have fostered a collaborative environment that encourages innovation and drives technological advancements.

Conclusion

Tatsuhiko Fujihira's innovative methods and dedication to semiconductor technology have established him as a key figure in the industry. His significant contributions, reflected in his extensive patent portfolio, continue to influence the evolution of semiconductor devices, ensuring improvements in efficiency and performance for modern applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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