Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Holdings Co., Ltd.

Fuji Electric Systems Co. Ltd.

Tatsuhiko Fujihira

Susumu Iwamoto

Yasuhiko Onishi

Takahiro Sato

Katsunori Ueno

Yasushi Miyasaka

Takashi Kobayashi

Kazuhiko Yoshida

Takeyoshi Nishimura

Tatsuji Nagaoka

Naoki Kumagai

Masaharu Nishiura

Shoichi Furuhata

Manabu Takei

Yukio Yano

Shigeyuki Takeuchi

Hitoshi Abe

Yasushi Niimura

Takeshi Ichimura

Masanori Inoue

Kazunori Oyabe

Shinichi Jimbo

Shigeyuki Obinata

Seiji Momota

Yoshihiro Ikura

Michiya Yamada

Shin Kiuchi

Motoi Kudoh

Kazutoshi Sugimura

Yuuichi Harada

Kenji Kunihara

Yasuhiko Ohnishi

Yuichi Harada

Masahito Otsuki

Mutsumi Kitamura

Tomoyuki Yamazaki

Akira Nishiura

Yoshihiko Nagayasu

Toshihiro Arai

Yoichi Ryokai

Naoki Yaezawa

Tetsuhiro Morimoto

Yoshiaki Minoya

Hiroshi Tobisaka

Ryu Saitou

Shouichi Furuhata

Youichi Shindou

Yoshiki Kondo

Masao Yoshino

Kumagai Naoki

A method of manufacturing a super-junction semiconductor device is disclosed that allows forming a high concentration layer with high precision and improves the trade-off relationship between the Eoff and the dV/dt. The method comprises a step of forming a parallel pn layer and a step of forming a proton irradiated layer in the upper region of the pn layer. Then, heat treatment is conducted on the proton irradiated layer for transforming the protons into donors to form a high concentration n type semiconductor layer.

Method of manufacturing a super-junction semiconductor device

A semiconductor device and method of manufacturing the semiconductor device is disclosed in which the tradeoff relationship between the Eoff and the turning OFF dV/dt is improved at a low cost using a trench embedding method. The method comprises a step of forming a parallel pn layer that is a superjunction structure using a trench embedding method and a step of ion implantation into an upper part of an n type semiconductor layer, i.e., an n type column, forming a high concentration n type semiconductor region. This method improves the trade-off relationship between the Eoff and the turning OFF dV/dt as compared with a high concentration n type semiconductor region formed of an epitaxial layer. This method achieves shorter process time and lower cost in manufacturing because it eliminates the redundant repeating of steps performed in the conventional method of forming a superjunction structure through multi-stage epitaxial growth.

Semiconductor device and method of manufacturing the same

A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

High power semiconductor device having a schottky barrier diode

A semiconductor device in includes a transistor and a surge absorption element such as Zener diode, that are formed on the same substrate and connected in parallel. The surge absorption element has a resistance during breakdown operation that is smaller than the resistance of the surge absorption element during breakdown operation of the transistor. In addition, the secondary breakdown current of the surge absorption element is larger than the secondary breakdown current of the transistor. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the surge absorption element and is limited to a voltage equal to or less than the breakdown voltage of the transistor, which would otherwise be destroyed.

Semiconductor device having transistor with high electro-static discharge capability and high noise capability

A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Diode and method for manufacturing the same

A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regionsand a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layerslaminated one by one epitaxially.

Semiconductor device with alternating conductivity type layer and method of manufacturing the same

A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Semiconductor device having a lateral MOSFET and combined IC using the same

A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region. With this structure, a high breakdown voltage semiconductor device is obtained at low cost, in which power elements, circuits for driving the power elements and logic elements for controlling the power elements are integrated together into the same chip.

High breakdown voltage junction terminating structure

Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

Super-junction semiconductor device and method of manufacturing the same

A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

Lateral super-junction semiconductor device

Growing community of inventors

Nagano, Japan

Tatsuhiko Fujihira