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For the Inventor, By the Inventor

Kawasaki, Japan

Takafumi Shimotori

This inventor holds 11 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2012-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takafumi Shimotori. Retrieved from https://idiyas.com/inventor/takafumi-shimotori

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 11

% Patents Active = 72.7

Average Co-Inventor Count = 4.0

ph-index = 3

Forward Citations = 22(Granted Patents)


Location History:

  • Kanagawa, JP (2012 - 2013)
  • Kanagawa-ken, JP (2012 - 2015)
  • Kawasaki, JP (2013 - 2015)

Company Filing History:

goldMedal11 out of 53,286 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 2012-2015

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11 patents (USPTO):Explore Patents
1. 9099180 - Semiconductor memory device (2015-08-04),
2. 9076525 - Semiconductor storage device and method of controlling data thereof (2015-07-07),
3. 8971090 - Semiconductor memory device (2015-03-03),
4. 8861265 - Semiconductor storage device and data control method thereof (2014-10-14),
5. 8837199 - Semiconductor memory device (2014-09-16),
6. 8675388 - Nonvolatile semiconductor memory device (2014-03-18),
7. 8605485 - Non-volatile semiconductor storage device and forming method (2013-12-10),
8. 8488367 - Semiconductor memory device and method for controlling the same (2013-07-16),
9. 8363448 - Semiconductor memory device (2013-01-29),
10. 8279655 - Non-volatile semiconductor memory device and method of controlling non-volatile semiconductor memory device (2012-10-02),
11. 8274822 - Nonvolatile memory device and method for driving same (2012-09-25),

Title: Takafumi Shimotori: Innovator in Semiconductor Technology

Introduction

Takafumi Shimotori is a prominent inventor based in Kawasaki, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 11 patents. His work focuses on enhancing the performance and efficiency of semiconductor memory devices.

Latest Patents

One of his latest patents is for a semiconductor memory device. This device includes a plurality of cell array blocks and a control circuit. The control circuit is designed to set a selected bit line to have 0 volts, while applying a first electric potential that is higher than 0 volts to a selected word line. Additionally, it applies a second electric potential, which is higher than 0 volts but lower than the first electric potential, to non-selected word lines. The control circuit also manages the electric potentials of non-selected bit lines to change the resistance status of the resistance variable film of the selected memory cell.

Another notable patent is for a semiconductor storage device and method of controlling data. This device features a memory cell array with memory cells that include variable resistive elements. The control circuit performs a set pulse applying operation to transition the variable resistive element from a high resistance state to a low resistance state. It also conducts a cure pulse applying operation, which applies a cure pulse with an opposite polarity to the set pulse, ensuring effective data management.

Career Highlights

Takafumi Shimotori is currently employed at Kabushiki Kaisha Toshiba, where he continues to innovate in semiconductor technology. His work has been instrumental in advancing the capabilities of memory devices, making them more efficient and reliable.

Collaborations

He has collaborated with notable coworkers, including Takayuki Tsukamoto and Hiroshi Kanno, contributing to various projects that enhance semiconductor technology.

Conclusion

Takafumi Shimotori's contributions to semiconductor technology through his patents and work at Toshiba highlight his role as a key innovator in the field. His advancements continue to shape the future of memory devices and their applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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