The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Aug. 29, 2012
Tomonori Kurosawa, Zama, JP;
Mizuki Kaneko, Yokohama, JP;
Takafumi Shimotori, Kawasaki, JP;
Takayuki Tsukamoto, Yokkaichi, JP;
Yoichi Minemura, Yokkaichi, JP;
Hiroshi Kanno, Yokkaichi, JP;
Tomonori Kurosawa, Zama, JP;
Mizuki Kaneko, Yokohama, JP;
Takafumi Shimotori, Kawasaki, JP;
Takayuki Tsukamoto, Yokkaichi, JP;
Yoichi Minemura, Yokkaichi, JP;
Hiroshi Kanno, Yokkaichi, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.