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For the Inventor, By the Inventor

San Jose, CA, United States of America

Subhash R Nariani

This inventor holds 20 USPTO granted patents, primarily in MOS Device Reliability. Top assignee: Vlsi Technology, Inc.. Active years: 1991-2000.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Subhash R Nariani. Retrieved from https://idiyas.com/inventor/subhash-r-nariani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20

% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 10

Forward Citations = 404(Granted Patents)


Location History:

  • Tracy, CA (US) (1991)
  • San Jose, CA (US) (1992 - 2000)

Company Filing History:

goldMedal20 out of 1,083 
 
Vlsi Technology, Inc.
 patents

Years Active: 1991-2000

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Areas of Expertise:
Dual Gate Oxide
MOS Devices
Silicon Rich Plasma
Wafer Level Prediction
Flash Memory Cell
Anti-Fuse Structure
Polysilicon Capacitor
Charge Build-Up
EEPROM Technology
Contamination Reduction
Cusp-Free Structures
Silicon-Enriched Oxide
20 patents (USPTO):Explore Patents
1. 6015732 - Dual gate oxide process with increased reliability (2000-01-18),
2. 5763937 - Device reliability of MOS devices using silicon rich plasma oxide films (1998-06-09),
3. 5638006 - Method and apparatus for wafer level prediction of thin oxide (1997-06-10),
4. 5602056 - Method for forming reliable MOS devices using silicon rich plasma oxide (1997-02-11),
5. 5587332 - Method of making flash memory cell (1996-12-24),
6. 5573970 - Method for reducing contamination of anti-fuse material in an anti-fuse (1996-11-12),
7. 5548224 - Method and apparatus for wafer level prediction of thin oxide reliability (1996-08-20),
8. 5493146 - Anti-fuse structure for reducing contamination of the anti-fuse material (1996-02-20),
9. 5492865 - Method of making structure for suppression of field inversion caused by (1996-02-20),
10. 5470775 - Method of forming a polysilicon-on-silicide capacitor (1995-11-28),
11. 5374833 - Structure for suppression of field inversion caused by charge build-up (1994-12-20),
12. 5371393 - EEPROM cell with improved tunneling properties (1994-12-06),
13. 5328865 - Method for making cusp-free anti-fuse structures (1994-07-12),
14. 5290734 - Method for making anti-fuse structures (1994-03-01),
15. 5290727 - Method for suppressing charge loss in EEPROMs/EPROMS and instabilities (1994-03-01),

Title: Subhash R Nariani - Pioneering Inventor from San Jose

Introduction: Subhash R Nariani is a distinguished inventor based in San Jose, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Subhash R Nariani holds several patents in the areas of artificial intelligence, machine learning, and cybersecurity, showcasing his commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Subhash R Nariani has worked with leading tech companies, spearheading research and development projects that have led to significant technological breakthroughs.

Collaborations: Throughout his career, Subhash R Nariani has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and knowledge sharing within the tech community.

Conclusion: Subhash R Nariani's relentless pursuit of innovation and his passion for creating cutting-edge technologies continue to inspire the next generation of inventors and tech enthusiasts worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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