The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 1996
Filed:
Jan. 20, 1995
Calvin T Gabriel, Cupertino, CA (US);
Subhash R Nariani, San Jose, CA (US);
VLSI Technology, Inc, San Jose, CA (US);
Abstract
An IC wafer containing thin oxide is fabricated with at least one pair of antenna structures having identical antenna ratio A.sub.R but different antenna plate areas. Each antenna structure includes connected-together conductive plate regions, one plate formed over thick field oxide and the other plate formed over thin oxide on the IC. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger antenna structure will overlie more weak oxide defects than will a smaller antenna structure. If wafer test leakage current across the larger antenna structure exceeds leakage current across the smaller antenna structure, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the area of the antenna plates. Because the A.sub.R ratios are constant, charge density is constant in the antenna structure portions overlying the thin oxide. If test leakage current on the wafer is substantially the same for each antenna structure, charge-damaged oxide is indicated because the damage is not area dependent. If desired, test MOS devices may be fabricated whose gates are the plates formed over the thin oxide. Defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices.