The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1996

Filed:

Jul. 14, 1994
Applicant:
Inventors:

Dipankar Pramanik, Saratoga, CA (US);

Subhash R Nariani, San Jose, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257530 ; 257 50 ; 257751 ; 257752 ; 257764 ;
Abstract

An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.


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