The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 1994
Filed:
Oct. 11, 1991
Applicant:
Inventors:
Subhash R Nariani, San Jose, CA (US);
Vivek Jain, Milpitas, CA (US);
Dipankar Pramanik, Cupertino, CA (US);
Kuang-Yeh Chang, Los Gatos, CA (US);
Assignee:
VLSI Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02L / ;
U.S. Cl.
CPC ...
257 52 ; 257409 ; 257499 ; 257646 ;
Abstract
The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
Nariani, Subhash. (1994). Structure for suppression of field inversion caused by charge build-up (U.S. Patent No. 5374833). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5374833
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile