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For the Inventor, By the Inventor

Milpitas, CA, United States of America

Vivek Jain

This inventor holds 15 USPTO granted patents. Top assignees: Vlsi Technology, Inc., Other. Active years: 1992-1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vivek Jain. Retrieved from https://idiyas.com/inventor/vivek-jain-5nql6zk6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 100.0

Average Co-Inventor Count = 3.3

ph-index = 9

Forward Citations = 317(Granted Patents)


Company Filing History:

goldMedal14 out of 1,083 
 
Vlsi Technology, Inc.
 patents
silverMedal1 out of 834,570 
Other
 patents

Years Active: 1992-1998

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15 patents (USPTO):Explore Patents
1. 5763937 - Device reliability of MOS devices using silicon rich plasma oxide films (1998-06-09),
2. 5602056 - Method for forming reliable MOS devices using silicon rich plasma oxide (1997-02-11),
3. 5522957 - Method for leak detection in etching chambers (1996-06-04),
4. 5496774 - Method improving integrated circuit planarization during etchback (1996-03-05),
5. 5492865 - Method of making structure for suppression of field inversion caused by (1996-02-20),
6. 5436410 - Method and structure for suppressing stress-induced defects in (1995-07-25),
7. 5403780 - Method enhancing planarization etchback margin, reliability, and (1995-04-04),
8. 5399533 - Method improving integrated circuit planarization during etchback (1995-03-21),
9. 5378318 - Planarization (1995-01-03),
10. 5374833 - Structure for suppression of field inversion caused by charge build-up (1994-12-20),
11. 5332868 - Method and structure for suppressing stress-induced defects in (1994-07-26),
12. 5328865 - Method for making cusp-free anti-fuse structures (1994-07-12),
13. 5290734 - Method for making anti-fuse structures (1994-03-01),
14. 5290727 - Method for suppressing charge loss in EEPROMs/EPROMS and instabilities (1994-03-01),
15. 5120679 - Anti-fuse structures and methods for making same (1992-06-09),

Title: Innovations by Vivek Jain in MOS Device Technology

Introduction

Vivek Jain is a prominent inventor based in Milpitas, CA, known for his significant contributions to the field of MOS (Metal-Oxide-Semiconductor) devices. With a total of 15 patents to his name, Jain has made remarkable advancements in device reliability and fabrication methods.

Latest Patents

Among his latest patents, Jain has developed innovative methods for enhancing the reliability of MOS devices using silicon-rich plasma oxide films. His inventions focus on the internal passivation of devices to suppress degradation from internal sources. The preferred embodiments of his patents include the formation of oxide layers enriched with silicon, which improve hot carrier lifetime. Additionally, Jain's methods for fabricating MOS devices with multilayer metallization involve modifying the composition of PECVD (Plasma-Enhanced Chemical Vapor Deposition) oxide films, as well as adjusting the location and thickness of these oxides.

Career Highlights

Throughout his career, Vivek Jain has worked with notable companies, including VLSI Technology, Inc. His expertise in the field has led to numerous innovations that have advanced the technology of MOS devices.

Collaborations

Jain has collaborated with esteemed colleagues such as Dipankar Pramanik and Subhash R. Nariani, contributing to the development of cutting-edge technologies in the semiconductor industry.

Conclusion

Vivek Jain's work in the field of MOS devices has significantly impacted the technology landscape, showcasing his dedication to innovation and excellence. His patents reflect a deep understanding of device reliability and fabrication methods, making him a key figure in the advancement of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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