The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 1992

Filed:

Jun. 04, 1991
Applicant:
Inventors:

William J Boardman, San Jose, CA (US);

David P Chan, San Ramon, CA (US);

Kuang-Yeh Chang, Los Gatos, CA (US);

Calvin T Gabriel, Pacifica, CA (US);

Vivek Jain, Milpitas, CA (US);

Subhash R Nariani, San Jose, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437195 ; 437 52 ; 437192 ; 437193 ; 437922 ; 148D / ;
Abstract

An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.


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