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For the Inventor, By the Inventor

Scotts Valley, CA, United States of America

Simon J S McElrea

This inventor holds 13 USPTO granted patents and 3 published patent applications. Top assignees: Adeia Semiconductor Bonding Technologies Inc., Vertical Circuits, Inc., Other. Active years: 2010-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Simon J S McElrea. Retrieved from https://idiyas.com/inventor/simon-j-s-mcelrea

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 13 

% Patents Active = 69.2

Average Co-Inventor Count = 4.8

ph-index = 6

Forward Citations = 189(Granted Patents)


Location History:

  • Scotta Valley, CA (US) (2011)
  • Scotts Valley, CA (US) (2010 - 2017)

Company Filing History:

goldMedal8 out of 1,911 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
silverMedal4 out of 10 
 
Vertical Circuits, Inc.
 patents
bronzeMedal1 out of 834,601 
Other
 patents

Years Active: 2010-2017

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13 patents (USPTO):Explore Patents
1. 9824999 - Semiconductor die mount by conformal die coating (2017-11-21),
2. 9305862 - Support mounted electrically interconnected die assembly (2016-04-05),
3. 9252116 - Semiconductor die mount by conformal die coating (2016-02-02),
4. 8742602 - Vertical electrical interconnect formed on support prior to die mount (2014-06-03),
5. 8723332 - Electrically interconnected stacked die assemblies (2014-05-13),
6. 8704379 - Semiconductor die mount by conformal die coating (2014-04-22),
7. 8680687 - Electrical interconnect for die stacked in zig-zag configuration (2014-03-25),
8. 8629543 - Electrically interconnected stacked die assemblies (2014-01-14),
9. 8324081 - Wafer level surface passivation of stackable integrated circuit chips (2012-12-04),
10. 8178978 - Support mounted electrically interconnected die assembly (2012-05-15),
11. 8159053 - Flat leadless packages and stacked leadless package assemblies (2012-04-17),
12. 7923349 - Wafer level surface passivation of stackable integrated circuit chips (2011-04-12),
13. 7843046 - Flat leadless packages and stacked leadless package assemblies (2010-11-30),

Title: The Innovative Journey of Simon J S McElrea

Introduction: Simon J S McElrea, a talented inventor based in Scotts Valley, CA, has made significant contributions to the field of technology with his creative and groundbreaking ideas.

Latest Patents: Simon J S McElrea holds several patents in various technological domains, showcasing his versatility and ingenuity in inventing new solutions to complex problems.

Career Highlights: Throughout his career, Simon J S McElrea has demonstrated a keen ability to identify gaps in the market and develop innovative products that meet the needs of consumers. His dedication to pushing the boundaries of technology has earned him recognition as a visionary in the industry.

Collaborations: Simon J S McElrea has collaborated with leading tech companies and research institutions to bring his inventions to life. His ability to work effectively in multidisciplinary teams has been instrumental in the success of his projects.

Conclusion: Simon J S McElrea's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors. His impact on the technological landscape is undeniable, and his legacy will undoubtedly endure for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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