The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2012
Filed:
Mar. 04, 2011
Simon J. S. Mcelrea, Scotts Valley, CA (US);
Terrence Caskey, Santa Cruz, CA (US);
Scott Mcgrath, Scotts Valley, CA (US);
Deann Eileen Melcher, San Jose, CA (US);
Reynaldo CO, Scotts Valley, CA (US);
Lawrence Douglas Andrews, Jr., Soquel, CA (US);
Weiping Pan, Santa Clara, CA (US);
Grant Villavicencio, Scotts Valley, CA (US);
Yong Du, Cupertino, CA (US);
Scott Jay Crane, Aromas, CA (US);
Zongrong Liu, Cupertino, CA (US);
Simon J. S. McElrea, Scotts Valley, CA (US);
Terrence Caskey, Santa Cruz, CA (US);
Scott McGrath, Scotts Valley, CA (US);
DeAnn Eileen Melcher, San Jose, CA (US);
Reynaldo Co, Scotts Valley, CA (US);
Lawrence Douglas Andrews, Jr., Soquel, CA (US);
Weiping Pan, Santa Clara, CA (US);
Grant Villavicencio, Scotts Valley, CA (US);
Yong Du, Cupertino, CA (US);
Scott Jay Crane, Aromas, CA (US);
Zongrong Liu, Cupertino, CA (US);
Other;
Abstract
An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).