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For the Inventor, By the Inventor

Mount Kisco, NY, United States of America

Shih-Hsien Lo

USPTO Granted Patents = 12

Average Co-Inventor Count = 4.0

ph-index = 4

Forward Citations = 36(Granted Patents)


Company Filing History:

goldMedal12 out of 164,197 
 
International Business Machines Corporation
 patents

Years Active: 2007-2018

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12 patents (USPTO):Explore Patents
1. 10083880 - Hybrid ETSOI structure to minimize noise coupling from TSV (2018-09-25),
2. 9653615 - Hybrid ETSOI structure to minimize noise coupling from TSV (2017-05-16),
3. 9087909 - Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSV (2015-07-21),
4. 8835997 - Low extension dose implants in SRAM fabrication (2014-09-16),
5. 8835191 - Nanowire stress sensors and stress sensor integrated circuits, design structures for a stress sensor integrated circuit, and related methods (2014-09-16),
6. 8822295 - Low extension dose implants in SRAM fabrication (2014-09-02),
7. 8614492 - Nanowire stress sensors, stress sensor integrated circuits, and design structures for a stress sensor integrated circuit (2013-12-24),
8. 8526219 - Enhanced static random access memory stability using asymmetric access transistors and design structure for same (2013-09-03),
9. 8381156 - 3D inter-stratum connectivity robustness (2013-02-19),
10. 8139400 - Enhanced static random access memory stability using asymmetric access transistors and design structure for same (2012-03-20),
11. 7342287 - Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures (2008-03-11),
12. 7274217 - High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs (2007-09-25),

Title: Shih-Hsien Lo: Innovator in Electronic Device Technology

Introduction

Shih-Hsien Lo is a prominent inventor based in Mount Kisco, NY (US), known for his significant contributions to electronic device technology. With a total of 12 patents to his name, he has made remarkable advancements in the field, particularly in minimizing noise coupling in electronic devices.

Latest Patents

One of Shih-Hsien Lo's latest patents is focused on a hybrid ETSOI structure designed to minimize noise coupling from through-silicon vias (TSVs). This innovative method involves patterning an ETSOI layer of an ETSOI wafer into segments, each ranging from about 3 nm to 20 nm in width. A gate electrode is formed over these segments, which serve as the channel region of a transistor. The segments extending from under the gate electrode function as the source and drain regions of the transistor. Additionally, at least one TSV is formed in the ETSOI wafer adjacent to the transistor, contributing to the overall functionality of the electronic device.

Career Highlights

Shih-Hsien Lo has established a successful career at International Business Machines Corporation (IBM), where he continues to push the boundaries of technology. His work has not only advanced the field of electronics but has also paved the way for future innovations in device design and functionality.

Collaborations

Throughout his career, Shih-Hsien Lo has collaborated with notable colleagues, including Jeffrey W Sleight and Chung-Hsun Lin. These partnerships have fostered a creative environment that encourages the exchange of ideas and the development of groundbreaking technologies.

Conclusion

Shih-Hsien Lo's contributions to electronic device technology exemplify the spirit of innovation. His work at IBM and his numerous patents highlight his dedication to advancing the field and improving electronic device performance.

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