The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2013

Filed:

Aug. 25, 2011
Applicants:

Michael P. Beakes, Yorktown Heights, NY (US);

Shih-hsien Lo, Mount Kisco, NY (US);

Michael R. Scheuermann, Katonah, NY (US);

Matthew R. Wordeman, Kula, HI (US);

Inventors:

Michael P. Beakes, Yorktown Heights, NY (US);

Shih-Hsien Lo, Mount Kisco, NY (US);

Michael R. Scheuermann, Katonah, NY (US);

Matthew R. Wordeman, Kula, HI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.


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