The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Jul. 19, 2005
Ching-te Chuang, South Salem, NY (US);
Koushik K. Das, Yorktown Heights, NY (US);
Shih-hsien Lo, Mount Kisco, NY (US);
Jeffrey W. Sleight, Ridgefield, CT (US);
Ching-Te Chuang, South Salem, NY (US);
Koushik K. Das, Yorktown Heights, NY (US);
Shih-Hsien Lo, Mount Kisco, NY (US);
Jeffrey W. Sleight, Ridgefield, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.