IDiyas

For the Inventor, By the Inventor

San Diego, CA, United States of America

Shayan Srinivasa Garani

USPTO Granted Patents = 13

Average Co-Inventor Count = 2.2

ph-index = 5

Forward Citations = 175(Granted Patents)


Location History:

  • Irvine, CA (US) (2013 - 2015)
  • San Diego, CA (US) (2011 - 2017)

Company Filing History:

goldMedal7 out of 2,867 
 
Stmicroelectronics Gmbh
 patents
silverMedal6 out of 5,310 
 
Western Digital Technologies, Inc.
 patents
bronzeMedal1 out of 5,553 
 
Stmicroelectronics S.r.l.
 patents
where one patent can have more than one assignee

Years Active: 2011-2017

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13 patents (USPTO):
1. 9837119 - Identifying a defect in a data-storage medium (2017-12-05),
2. 9324370 - Identifying a defect in a data-storage medium (2016-04-26),
3. 9214963 - Method and system for monitoring data channel to enable use of dynamically adjustable LDPC coding parameters in a data storage system (2015-12-15),
4. 9203434 - Systems and methods for improved encoding of data in data storage devices (2015-12-01),
5. 8990668 - Decoding data stored in solid-state memory (2015-03-24),
6. 8913336 - Constrained on-the-fly interleaver address generator circuits, systems, and methods (2014-12-16),
7. 8856615 - Data storage device tracking log-likelihood ratio for a decoder based on past performance (2014-10-07),
8. 8760782 - Methods and devices for joint two-dimensional self-iterating equalization and detection (2014-06-24),
9. 8582223 - Methods and devices for two-dimensional iterative multi-track based map detection (2013-11-12),
10. 8397125 - Encoding apparatus, system, and method using low density parity check (LDPC) codes (2013-03-12),
11. 8290102 - Adaptive data dependent noise prediction (ADDNP) (2012-10-16),
12. 8255768 - Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords (2012-08-28),
13. 8055973 - Channel constrained code aware interleaver (2011-11-08),
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