The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Jun. 05, 2009
Applicants:

Shayan Srinivasa Garani, San Diego, CA (US);

Nicholas J. Richardson, San Diego, CA (US);

Xinde HU, San Diego, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Inventors:

Shayan Srinivasa Garani, San Diego, CA (US);

Nicholas J. Richardson, San Diego, CA (US);

Xinde Hu, San Diego, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Assignee:

STMicroelectronics, Inc., Coppell, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.


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