Stmicroelectronics Gmbh

Western Digital Technologies, Inc.

Stmicroelectronics S.r.l.

Shayan Srinivasa Garani

Sivagnanam Parthasarathy

Kent Douglas Anderson

Anantha Raman Krishnan

Xinde Hu

Shafa Dahandeh

Yiming Chen

Mustafa Nazmi Kaynak

Andrew John Tomlin

Richard David Barndt

Nicholas Julian Richardson

Anthony Dwayne Weathers

Guangming Lu

Stefano Valle

Sudha Thipparthi

An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.

Identifying a defect in a data-storage medium

A data storage system configured to adaptively code data and related methods are disclosed. In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller includes a channel monitor that determines the quality of read signals from the pages when they are read, and provides adjustment metrics to aid in the selection of a code rate, such as a code rate for a low-density parity-check (LDPC) code. In this way, the code rate used for data encoding can be dynamically adjusted to accommodate degradation of the non-volatile memory array over its useable life.

Method and system for monitoring data channel to enable use of dynamically adjustable LDPC coding parameters in a data storage system

Some embodiments of the invention are directed to systems and methods for an optimized and efficient encoding scheme that can accommodate higher block lengths of data. Some embodiments generally relate to: (1) coding structures for a new class of LDPC matrices based on algebraic relations, and (2) encoding method that achieves the R=1&#x2212;k/n exact bound on code rate. In addition, in some embodiments, the coding structures efficiently create matrices with excellent error-correcting properties and are devoid of short cycles (leading to robust performance). The implementations of the coding structures are scalable over a range of code rates and block lengths.

Systems and methods for improved encoding of data in data storage devices

Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.

Decoding data stored in solid-state memory

An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.

Constrained on-the-fly interleaver address generator circuits, systems, and methods

A data storage device is disclosed comprising a non-volatile memory (NVM). First data is written to a first area of the NVM, and a first estimated data sequence is read from the first area of the NVM. The first estimated data sequence is first decoded, and a log-likelihood ratio (LLR) is first updated based on the first decode. Second data is written to a second area of the NVM, and a second estimated data sequence is read from the second area of the non-volatile memory. The second estimated data sequence is second decoded in response to the first updated LLR, and the LLR is second updated based on the second decode.

Data storage device tracking log-likelihood ratio for a decoder based on past performance

A disk drive is configured to decode data written over a plurality of data tracks using joint self-iterating soft equalization and an iterative turbo 2-D MAP-based detection, by performing soft self-iterating linear 2-D MMSE equalization on received input samples; computing MMSE estimates for coefficients of a 2-D equalization filter based on a-priori values, mean of the a-priori values, the 2-D filter and the received input samples; updating the coefficients of the 2-D filter using a variance based on the a-priori values when carrying out a first iteration and based on an extrinsic LLR when carrying out subsequent iterations; determining values of the individual bits in the input samples using the updated coefficients; computing an output LLR of each individual received sample based on the computed MMSE estimate, the mean and the variance, and computing the extrinsic LLR by subtracting a priori LLR from the output LLR.

Methods and devices for joint two-dimensional self-iterating equalization and detection

Decoding data written over a plurality of tracks includes selecting a mask that accounts for Inter-Symbol-Interference, the mask including channel coefficients and defining a trellis defining a plurality of states; receiving a signal corresponding to an input pixel from each of the plurality of tracks and generating equalized samples therefrom; computing transition branch probabilities for each input vector based on a Gaussian noise distribution using the equalized samples, ideal samples and a priori probabilities of the input vector; computing forward and backward probabilities via recursions using the computed transition branch probabilities; combining the forward, backward and transition branch probabilities to generate a-posteriori probabilities for the input vector; marginalizing the a-posteriori probabilities over values of neighboring pixels to generate an a-posteriori probability for a pixel of the input vector in a given state, and decoding the pixel as a first or second logical state from the marginalized a-posteriori probabilities.

Methods and devices for two-dimensional iterative multi-track based map detection

A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix.

Encoding apparatus, system, and method using low density parity check (LDPC) codes

A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and the adapted one or more filter coefficients.

Adaptive data dependent noise prediction (ADDNP)

To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords

An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

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San Diego, CA, United States of America

Shayan Srinivasa Garani