Noida, India

Sandeep Jain

This inventor holds 20 USPTO granted patents and 3 published patent applications and 2 EPO patents, primarily in Scan Test Optimization. Top assignees: Stmicroelectronics International N.v., Nxp USA, Inc., Freescale Semiconductor,inc.. Active years: 2008-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sandeep Jain. Retrieved from https://idiyas.com/inventor/sandeep-jain-m8hb2szd

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20 

% Patents Active = 80.0

 

Average Co-Inventor Count = 2.4

ph-index = 3

Forward Citations = 32(Granted Patents)


Location History:

  • Rewari, IN (2008 - 2013)
  • Ghaziabad, IN (2015 - 2021)
  • Noida, IN (2019 - 2023)

Company Filing History:


Years Active: 2008-2025

Loading Chart...
Loading Chart...
Areas of Expertise:
Scan Compression
Test Time Reduction
Redundancy Circuit
Secure Communication
Fault Attack Protection
Idle Loop Detection
Debugging Techniques
Data Dependency Tracing
Signature Analysis
Multi-Threaded Systems
Atomic Binary Translations
Side Channel Attack Protection
20 patents (USPTO):Explore Patents

Title: Innovations by Sandeep Jain

Introduction

Sandeep Jain, located in Noida, India, is a prominent inventor recognized for his significant contributions to the field of digital circuit design and testing. With a total of 19 patents to his name, Jain's work focuses on reducing test times and optimizing circuit performance, showcasing his innovative approach to solving complex engineering challenges.

Latest Patents

Among Jain's latest patents is the "Partial Chain Reconfiguration for Test Time Reduction." This invention outlines a method for testing a scan chain by segmenting it into multiple parts and utilizing multiplexers to rearrange the segments strategically. This process allows for efficient communication of test patterns and accurate fault determination.

Another notable patent by Jain is "Test Time Reduction in Circuits with Redundant Flip-Flops." This patent details a digital circuit design with redundant flip-flops that can switch between functional and test modes, allowing for effective fault detection. By optimizing the arrangement of flip-flops and data signals, the patent contributes significantly to enhancing test efficiency.

Career Highlights

Sandeep Jain has worked with esteemed companies such as STMicroelectronics International N.V. and NXP USA Inc., where he has contributed to various innovative projects. His expertise in digital circuit testing and design has positioned him as a valuable asset in these organizations, driving advancements in technology.

Collaborations

Throughout his career, Jain has collaborated with talented professionals in the field, including Shalini Pathak and Nikila Krishnamoorthy. These collaborations have further enriched his work, leading to breakthroughs in circuit design and testing methodologies.

Conclusion

Sandeep Jain's contributions to innovation and invention in the realm of digital circuits have cemented his reputation as a leading inventor. With numerous patents to his name and ongoing advancements in technology, Jain continues to inspire future innovations in the engineering domain.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…