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For the Inventor, By the Inventor

Los Gatos, CA, United States of America

Praful Jain

This inventor holds 16 USPTO granted patents and 1 published patent application and 2 EPO patents. Top assignee: Xilinx, Inc.. Active years: 2015-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Praful Jain. Retrieved from https://idiyas.com/inventor/praful-jain

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16 

% Patents Active = 93.8

 

Average Co-Inventor Count = 2.2

ph-index = 5

Forward Citations = 104(Granted Patents)


Location History:

  • Ghaziabad, IN (2015 - 2016)
  • Los Gatos, CA (US) (2015 - 2017)
  • Leuven, BE (2017)
  • San Jose, CA (US) (2021 - 2024)

Company Filing History:

goldMedal16 out of 5,108 
 
Xilinx, Inc.
 patents

Years Active: 2015-2026

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16 patents (USPTO):Explore Patents
1. 12748909 - Systems and methods for machine learning based voltage drop prediction for a 3D stacked device (2026-09-29),
2. 11961823 - Forming and/or configuring stacked dies (2024-04-16),
3. 11670585 - Power distribution for active-on-active die stack with reduced resistance (2023-06-06),
4. 11270977 - Power delivery network for active-on-active stacked integrated circuits (2022-03-08),
5. 11043480 - Forming and/or configuring stacked dies (2021-06-22),
6. 11041211 - Power distribution for active-on-active die stack with reduced resistance (2021-06-22),
7. 10908598 - Integrated circuits designed for multiple sets of criteria (2021-02-02),
8. 9825632 - Circuit for and method of preventing multi-bit upsets induced by single event transients (2017-11-21),
9. 9628081 - Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit (2017-04-18),
10. 9484919 - Selection of logic paths for redundancy (2016-11-01),
11. 9483599 - Circuit design-specific failure in time rate for single event upsets (2016-11-01),
12. 9281807 - Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit (2016-03-08),
13. 9236353 - Integrated circuit having improved radiation immunity (2016-01-12),
14. 9183338 - Single-event upset mitigation in circuit design for programmable integrated circuits (2015-11-10),
15. 9054684 - Single event upset enhanced architecture (2015-06-09),

Title: Praful Jain: Pioneering Inventor from Los Gatos

Introduction: Praful Jain is a distinguished inventor based in Los Gatos, California, known for his groundbreaking contributions to various technological fields.

Latest Patents: Praful Jain holds several patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his versatility and innovative spirit.

Career Highlights: With a career spanning over two decades, Praful Jain has worked with leading tech companies, research institutions, and universities, consistently pushing the boundaries of innovation.

Collaborations: Praful Jain has collaborated with top engineers, scientists, and researchers worldwide, fostering a culture of creativity and excellence in all his projects.

Conclusion: Praful Jain's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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