The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
Sep. 23, 2014
Xilinx, Inc., San Jose, CA (US);
Praful Jain, Los Gatos, CA (US);
James Karp, Saratoga, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.