The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2016
Filed:
Jun. 09, 2014
Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Pierre Maillard, San Jose, CA (US);
Praful Jain, Los Gatos, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Sundeep Ram Gopal Agarwal, Hyderabad, IN;
Austin H. Lesea, Los Gatos, CA (US);
Jun Liu, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/023 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/0372 (2013.01);
Abstract
A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.