IDiyas

For the Inventor, By the Inventor

Campbell, CA, United States of America

Pierre Maillard

USPTO Granted Patents = 14


Average Co-Inventor Count = 3.0

ph-index = 3

Forward Citations = 30(Granted Patents)


Location History:

  • San Jose, CA (US) (2015 - 2019)
  • Campbell, CA (US) (2017 - 2023)

Company Filing History:

goldMedal14 out of 5,002 
 
Xilinx, Inc.
 patents
silverMedal1 out of 12,867 
 
Advanced Micro Devices Corporation
 patents
where one patent can have more than one assignee

Years Active: 2015-2025

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14 patents (USPTO):
1. 12346226 - System and method for SEU detection and correction (2025-07-01),
2. 11652481 - Designing single event upset latches (2023-05-16),
3. 10958067 - Single event latch-up (SEL) mitigation detect and mitigation (2021-03-23),
4. 10861848 - Single event latch-up (SEL) mitigation techniques (2020-12-08),
5. 10574214 - Circuit for and method of storing data in an integrated circuit device (2020-02-25),
6. 10366999 - Single event upset (SEU) mitigation for FinFET technology using fin topology (2019-07-30),
7. 10263623 - Circuit for and method of storing data in an integrated circuit device (2019-04-16),
8. 10033388 - Circuit for and method of enabling the selection of a circuit (2018-07-24),
9. 9825632 - Circuit for and method of preventing multi-bit upsets induced by single event transients (2017-11-21),
10. 9793899 - Mitigation of single event latchup (2017-10-17),
11. 9484919 - Selection of logic paths for redundancy (2016-11-01),
12. 9281807 - Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit (2016-03-08),
13. 9236354 - Integrated circuit package with thermal neutron shielding (2016-01-12),
14. 9183338 - Single-event upset mitigation in circuit design for programmable integrated circuits (2015-11-10),
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