Xilinx, Inc.

Advanced Micro Devices Corporation

Pierre Maillard

Michael J Hart

Praful Jain

Yanran Chen

Austin H Lesea

James Karp

Jun Liu

Martin L Voogel

John J Wuu

Santosh Yachareni

John K Jennings

Kumar Rahul

Sundeep Ram Gopal Agarwal

Mohammed Fakhruddin

Robert I Fu

Betty Y Lau

Jeffrey Barton

Mrinmoy Goswami

Tabrez Alam

Md Hussain

Sanat Kumar Dubey

Gokul Puthenpurayil Ravindran

Mini Rawat

Jue Arver

Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

System and method for SEU detection and correction

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

Designing single event upset latches

An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

Single event latch-up (SEL) mitigation detect and mitigation

Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

Single event latch-up (SEL) mitigation techniques

A circuit for storing data in an integrated circuit is described. The circuit comprises an input adapted to receive the data; a memory element coupled to the input, the memory element comprising a storage node for storing the data; at least one node that is separate from the storage node for storing the data; and at least a portion of a dummy transistor coupled to the at least one node that is separate from the storage node for storing the data. A method of storing data in an integrated circuit is also described.

Circuit for and method of storing data in an integrated circuit device

Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (H) and a width W. The height (H) is greater than an optimal height (H), wherein the height His a height that would optimize speed of a FinFET transistor having the width W.

Single event upset (SEU) mitigation for FinFET technology using fin topology

A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described.

An integrated circuit enables the selection of a circuit. According to one implementation, a plurality of redundant circuits provide a predetermined function and a voltage sensor may be coupled to receive a reference voltage. A selection circuit may be coupled to the voltage sensor and the reference voltage, wherein the selection circuit selects one of the plurality of redundant circuits to be implemented in the integrated circuit based upon a detected voltage of the reference voltage of the reference voltage.

Circuit for and method of enabling the selection of a circuit

A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

Circuit for and method of preventing multi-bit upsets induced by single event transients

The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

Mitigation of single event latchup

Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

Selection of logic paths for redundancy

A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.

Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit

A semiconductor package with thermal neutron shielding is disclosed. The semiconductor package includes a substrate and an integrated circuit die disposed on the substrate. The semiconductor package also has a thermal neutron shield including a shielding material. The shielding material includes boron-10 and is configured to inhibit a portion of thermal neutrons that encounter the thermal neutron shield from passing through the thermal neutron shield.

Integrated circuit package with thermal neutron shielding

In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.

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Campbell, CA, United States of America

Pierre Maillard