The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Oct. 04, 2023
Applicants:

Xilinx, Inc., San Jose, CA (US);

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Kumar Rahul, Hyderabad, IN;

Santosh Yachareni, Hyderabad, IN;

Pierre Maillard, Campbell, CA (US);

Mrinmoy Goswami, Hyderabad, IN;

Tabrez Alam, Hyderabad, IN;

Gokul Puthenpurayil Ravindran, Hyderabad, IN;

Md Hussain, Hyderabad, IN;

Sanat Kumar Dubey, Hyderabad, IN;

John J. Wuu, Fort Collins, CO (US);

Assignees:

XILINX, INC., San Jose, CA (US);

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/16 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/167 (2013.01); G06F 11/0772 (2013.01); G06F 11/1608 (2013.01);
Abstract

Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.


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