Fort Collins, CO, United States of America

John J Wuu

This inventor holds 54 USPTO granted patents and 29 published patent applications and 4 EPO patents, primarily in 3D Stacked Memory. Top assignees: Advanced Micro Devices Corporation, Hewlett-Packard Development Company, L.p., Xilinx, Inc.. Active years: 2001-2026.

USPTO Granted Patents = 54 (Patent Applications = 29)

% Patents Active = 88.9

EPO Patents = 4 (Patent Applications = 8)

Average Co-Inventor Count = 3.1

ph-index = 6

Forward Citations = 141(Granted Patents)

Forward Citations (Not Self Cited) = 123(Dec 10, 2025)

Location History:

Ft Collins, CO (US) (2001 - 2002)
Ft. Collins, CO (US) (2018 - 2023)
Fort Collins, CO (US) (2001 - 2024)

Company Filing History:

42 out of 13,146

Advanced Micro Devices Corporation

patents

4 out of 27,650

Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

patents

7. 1 out of 834,307

Other

patents

where one patent can have more than one assignee

Years Active: 2001-2026

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Areas of Expertise:

3D Die Stacking

Thermal Management

Single Event Upset

Low Power Cache

Through-Silicon Via

SRAM

Memory Optimization

Voltage Synchronization

Bitcell Design

Memory Array

Electrostatic Discharge

Dynamic Timing

54 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12713624 - BACKSIDE POWERTD (2026-08-18),

2. 12696736 - Chip-on-wafer face-to-back hybrid bonding without support carrier (2026-07-28),

3. 12575449 - Backside power delivery and power grid pattern to support 3D die stacking (2026-03-10),

4. 12531409 - Apparatus, system, and method for reducing the footprints of circuits that protect against the antenna effect and electrostatic discharge (2026-01-20),

5. 12445120 - Dynamic setup and hold times adjustment for memories (2025-10-14),

6. 12414283 - Devices and systems for flying bitline with jumper cell (2025-09-09),

7. 12346226 - System and method for SEU detection and correction (2025-07-01),

8. 12266585 - Arrangement and thermal management of 3D stacked dies (2025-04-01),

9. 12212337 - ECC optimization (2025-01-28),

10. 12165700 - SRAM power savings and write assist (2024-12-10),

11. 12107076 - Through-silicon via layout for multi-die integrated circuits (2024-10-01),

12. 12073919 - Dual read port latch array bitcell (2024-08-27),

13. 12045469 - Single event upset tolerant memory device (2024-07-23),

14. 12033721 - Split read port latch array bit cell (2024-07-09),

15. 11869874 - Stacked die circuit routing system and method (2024-01-09),

Title: The Innovative Journey of John J Wuu

Introduction: John J Wuu, a talented inventor based in Fort Collins, CO (US), has made significant contributions to the field of innovations with his creative mindset and dedication.

Latest Patents: John J Wuu holds several patents in various technological areas, showcasing his versatility and expertise in inventing cutting-edge solutions to complex problems.

Career Highlights: Throughout his career, John J Wuu has demonstrated a remarkable ability to transform ideas into tangible inventions that have the potential to impact industries and improve people's lives. His innovative spirit and passion for creating have led to the development of groundbreaking technologies.

Collaborations: John J Wuu has collaborated with leading research institutions, universities, and companies to further his inventions and bring them to the market. His collaborative efforts have resulted in successful partnerships that have accelerated the innovation process.

Conclusion: John J Wuu's journey as an inventor is a testament to his unwavering commitment to pushing the boundaries of what is possible through innovation. His remarkable achievements and groundbreaking inventions continue to inspire the next generation of inventors and shape the future of technology.