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For the Inventor, By the Inventor

Fort Collins, CO, United States of America

John J Wuu

USPTO Granted Patents = 50 

 

Average Co-Inventor Count = 3.1

ph-index = 6

Forward Citations = 133(Granted Patents)

Forward Citations (Not Self Cited) = 123(Dec 10, 2025)


Location History:

  • Ft Collins, CO (US) (2001 - 2002)
  • Ft. Collins, CO (US) (2018 - 2023)
  • Fort Collins, CO (US) (2001 - 2024)

Company Filing History:

goldMedal38 out of 12,883 
 
Advanced Micro Devices Corporation
 patents
silverMedal4 out of 27,412 
 
Hewlett-packard Development Company, L.P.
 patents
bronzeMedal3 out of 5,671 
 
Globalfoundries Inc.
 patents
4. 3 out of 9,638 
 
Hewlett-packard Company
 patents
5. 3 out of 5,008 
 
Xilinx, Inc.
 patents
6. 3 out of 1,041 
 
Ati Technologies Ulc
 patents
7. 1 out of 832,843 
Other
 patents
where one patent can have more than one assignee

Years Active: 2001-2025

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Areas of Expertise:
Dynamic Memory Adjustment
3D Stacked Dies
Single Event Upset Tolerance
Error Detection Devices
Through-Silicon Via Technology
Low Power Cache
SRAM Power Savings
Memory Array Test Logic
Programmable Write Modes
In-Memory Logic Functions
Multi-Port SRAM Design
Thermal Management Solutions
50 patents (USPTO):Explore Patents
1. 12445120 - Dynamic setup and hold times adjustment for memories (2025-10-14),
2. 12414283 - Devices and systems for flying bitline with jumper cell (2025-09-09),
3. 12346226 - System and method for SEU detection and correction (2025-07-01),
4. 12266585 - Arrangement and thermal management of 3D stacked dies (2025-04-01),
5. 12212337 - ECC optimization (2025-01-28),
6. 12165700 - SRAM power savings and write assist (2024-12-10),
7. 12107076 - Through-silicon via layout for multi-die integrated circuits (2024-10-01),
8. 12073919 - Dual read port latch array bitcell (2024-08-27),
9. 12045469 - Single event upset tolerant memory device (2024-07-23),
10. 12033721 - Split read port latch array bit cell (2024-07-09),
11. 11869874 - Stacked die circuit routing system and method (2024-01-09),
12. 11822484 - Low power cache (2023-11-21),
13. 11804479 - Scheme for enabling die reuse in 3D stacked products (2023-10-31),
14. 11715514 - Latch bit cells (2023-08-01),
15. 11710698 - Dual-track bitline scheme for 6T SRAM cells (2023-07-25),

Title: The Innovative Journey of John J Wuu

Introduction: John J Wuu, a talented inventor based in Fort Collins, CO (US), has made significant contributions to the field of innovations with his creative mindset and dedication.

Latest Patents: John J Wuu holds several patents in various technological areas, showcasing his versatility and expertise in inventing cutting-edge solutions to complex problems.

Career Highlights: Throughout his career, John J Wuu has demonstrated a remarkable ability to transform ideas into tangible inventions that have the potential to impact industries and improve people's lives. His innovative spirit and passion for creating have led to the development of groundbreaking technologies.

Collaborations: John J Wuu has collaborated with leading research institutions, universities, and companies to further his inventions and bring them to the market. His collaborative efforts have resulted in successful partnerships that have accelerated the innovation process.

Conclusion: John J Wuu's journey as an inventor is a testament to his unwavering commitment to pushing the boundaries of what is possible through innovation. His remarkable achievements and groundbreaking inventions continue to inspire the next generation of inventors and shape the future of technology.

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