The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Sep. 29, 2023
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Chandra Sekhar Mandalapu, Ft. Collins, CO (US);

Raja Swaminathan, Austin, TX (US);

Liwei Wang, Austin, TX (US);

John Wuu, Ft. Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H10P 72/70 (2026.01); H10P 90/00 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10P 90/1914 (2026.01); H10P 72/74 (2026.01); H10W 72/019 (2026.01); H10W 72/01938 (2026.01); H10W 72/0198 (2026.01);
Abstract

A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.


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