The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2019
Filed:
Mar. 31, 2016
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventor:
Pierre Maillard, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1116 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 29/0847 (2013.01); H01L 29/7851 (2013.01);
Abstract
Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (H) and a width W. The height (H) is greater than an optimal height (H), wherein the height His a height that would optimize speed of a FinFET transistor having the width W.