The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2017
Filed:
Aug. 04, 2016
Xilinx, Inc., San Jose, CA (US);
Pierre Maillard, San Jose, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Praful Jain, Leuven, BE;
Robert I. Fu, Saratoga, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.