Pradeep R Trivedi

This inventor holds 76 USPTO granted patents and 1 EPO patent, primarily in Integrated Circuit Design (CPC class G06F). Top assignees: Sun Microsystems, Inc., Apple Inc.. Active years: 2002-2021.

USPTO Granted Patents = 76

% Patents Active = 88.2

EPO Patents = 1 (Patent Applications = 1)

Average Co-Inventor Count = 3.2

ph-index = 11

Forward Citations = 511(Granted Patents)

Forward Citations (Not Self Cited) = 464(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Sunnyvale, CA (US) (2002 - 2012)
Saratoga, CA (US) (2013 - 2021)

Company Filing History:

68 out of 7,642

Sun Microsystems, Inc.

Years Active: 2002-2021

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Areas of Expertise:

Delay Locked Loop

Clock Gating

Aging Compensation

Low Latency Circuit

Phase Locked Loop

Voltage Drop Budgets

Signal Delay Measurement

Temperature Sensor

I/O Interface Driver

Calibration Technique

Jitter Estimation

Power Supply Noise

76 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11023403 - Chip to chip interface with scalable bandwidth (2021-06-01),

2. 10521391 - Chip to chip interface with scalable bandwidth (2019-12-31),

3. 10241537 - Digital on-chip duty cycle monitoring device (2019-03-26),

4. 8373470 - Modular programmable delay line blocks for use in a delay locked loop (2013-02-12),

5. 8368444 - Delay locked loop including a mechanism for reducing lock time (2013-02-05),

6. 8341578 - Clock gater with test features and low setup time (2012-12-25),

7. 8026754 - Low latency flop circuit (2011-09-27),

8. 7779372 - Clock gater with test features and low setup time (2010-08-17),

9. 7263628 - Method and apparatus for receiver circuit tuning (2007-08-28),

10. 7251305 - Method and apparatus to store delay locked loop biasing parameters (2007-07-31),

11. 7129800 - Compensation technique to mitigate aging effects in integrated circuit components (2006-10-31),

12. 7106113 - Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver (2006-09-12),

13. 7054787 - Embedded integrated circuit aging sensor system (2006-05-30),

14. 6998887 - Calibration technique for phase locked loop leakage current (2006-02-14),

15. 6976235 - Region-based voltage drop budgets for low-power design (2005-12-13),

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**Title: The Innovative Mind of Pradeep R Trivedi**

Introduction:

Pradeep R Trivedi, a distinguished inventor based in Sunnyvale, CA (US), has made significant contributions to the field of technology with a remarkable portfolio of 76 patents. His forward-thinking approach and ingenuity have led to groundbreaking innovations in chip-to-chip interface technology.

Latest Patents:

Among his latest patents is the "Chip to Chip Interface with Scalable Bandwidth." This cutting-edge system and method revolutionize the transportation of data across lanes in a computing system. By efficiently managing bandwidth requirements and dynamically adjusting data rates, this invention enhances data transmission speed and reliability.

Career Highlights:

Pradeep R Trivedi has garnered extensive experience working with industry giants such as Sun Microsystems, Inc., and Apple Inc. His expertise and technical acumen have been instrumental in developing advanced technologies that drive innovation and progress in the tech industry.

Collaborations:

Throughout his career, Pradeep R Trivedi has collaborated with notable professionals in the field, including Claude R Gauthier and Dean Liu. Together, they have synergized their skills and knowledge to push the boundaries of technological advancements and achieve remarkable milestones.

Conclusion:

In conclusion, Pradeep R Trivedi stands as a visionary inventor who continues to push the boundaries of technological innovation. With a plethora of patents to his name and a track record of collaboration with industry leaders, he remains at the forefront of cutting-edge technological advancements that shape the future of the industry.

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