The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Jun. 14, 2017
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Huaimin Li, San Jose, CA (US);

Fabien S Faure, Santa Clara, CA (US);

Shy Hamami, Ganei-Tikva, IL;

Pradeep Trivedi, Saratoga, CA (US);

Yaron Cohen, Kfar-Saba, IL;

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01); H03K 5/156 (2006.01); G01D 5/24 (2006.01); G06F 1/08 (2006.01); H03K 21/08 (2006.01); H03K 5/04 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 3/017 (2013.01); H03K 5/04 (2013.01); H03K 21/08 (2013.01); H03K 2005/00019 (2013.01);
Abstract

An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.


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