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For the Inventor, By the Inventor

Shanhua, Taiwan

Pin Chia Su

This inventor holds 25 USPTO granted patents and 5 published patent applications, primarily in Semiconductor Manufacturing. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., National Yang Ming Chiao Tung University, Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2004-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pin Chia Su. Retrieved from https://idiyas.com/inventor/pin-chia-su

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 68.0

Average Co-Inventor Count = 5.1

ph-index = 4

Forward Citations = 73(Granted Patents)


Location History:

  • Kaohsiung, TW (2004)
  • Shanhua Township, Tainan County, TW (2007)
  • Tainan, TW (2006 - 2009)
  • Shanhua, TW (2014 - 2016)
  • Jhubei, TW (2016)
  • Shanhua Township, TW (2011 - 2022)
  • Hsinchu County, TW (2012 - 2023)
  • Tainan County, TW (2011 - 2024)

Company Filing History:

goldMedal22 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal4 out of 1,247 
 
National Yang Ming Chiao Tung University
 patents
bronzeMedal1 out of 481 
 
Taiwan Semiconductor Manufacturing Co., Ltd.
 patents
where one patent can have more than one assignee

Years Active: 2004-2026

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Areas of Expertise:
SRAM Circuits
Metal Gate Structures
Backside Illumination
Field-Effect Transistors
Photodiodes
Gate Electrode
Hybrid TFET-MOSFET
Critical Dimension Control
Plasma Treatment
Chemical Bath Stability
FinFET SRAM Cell
Xenon Dilution Gas
25 patents (USPTO):Explore Patents
1. 12626746 - Method for manufacturing SRAM memory circuit (2026-05-12),
2. 12507429 - Metal gate structures and methods of fabricating the same in field-effect transistors (2025-12-23),
3. 12464801 - Circuit structure with gate configuration (2025-11-04),
4. 12113120 - Gate electrode having a work-function layer including materials with different average grain sizes (2024-10-08),
5. 12021130 - Circuit structure with gate configuration (2024-06-25),
6. 11949000 - Metal gate structures and methods of fabricating the same in field-effect transistors (2024-04-02),
7. 11631447 - Memory circuit and manufacturing method thereof (2023-04-18),
8. 11588038 - Circuit structure with gate configuration (2023-02-21),
9. 11502185 - Methods of manufacturing a gate electrode having metal layers with different average grain sizes (2022-11-15),
10. 11476351 - Metal gate structures and methods of fabricating the same in field-effect transistors (2022-10-18),
11. 9450014 - Backside illumination image sensor chips and methods for forming the same (2016-09-20),
12. 9412439 - Hybrid TFET-MOSFET circuit design (2016-08-09),
13. 9240503 - Methods of manufacturing and using a photodiode with concave reflector (2016-01-19),
14. 9142588 - Backside illumination image sensor chips and methods for forming the same (2015-09-22),
15. 8884390 - Backside illumination image sensor chips and methods for forming the same (2014-11-11),

Title: Innovations and Contributions of Pin Chia Su

Introduction

Pin Chia Su, based in Shanhua, Taiwan, is an accomplished inventor with a remarkable portfolio of 22 patents. His work primarily focuses on advancements in semiconductor technology, contributing significantly to the field through innovative designs and methodologies.

Latest Patents

Among his recent inventions, Pin Chia Su has developed several noteworthy patents. One of his latest patents, titled "Gate electrode having a work-function layer including materials with different average grain sizes," outlines a sophisticated method that involves forming a dummy gate stack over a semiconductor region and subsequently creating a replacement gate dielectric and electrode. This method enhances the performance and efficiency of semiconductor devices by optimizing the grain sizes of the materials used. Another one of his significant patents is related to a "Circuit structure with gate configuration." This patent discloses a semiconductor structure that integrates first and second transistors, with distinct gate configurations to cater to different circuit requirements, thereby improving overall functionality and performance in high-frequency applications.

Career Highlights

Throughout his career, Pin Chia Su has made substantial contributions to both academic and corporate settings. He has worked with prominent institutions, including Taiwan Semiconductor Manufacturing Company Limited and National Chiao Tung University. His dual experience in academia and industry underscores his commitment to advancing technology and fostering innovation.

Collaborations

Pin Chia Su has collaborated with several noteworthy professionals, including Ru-Shang Hsiao and Ying Hsin Lu. These partnerships highlight the collaborative nature of innovation and research, allowing for a synergy that enhances the potential for groundbreaking developments in semiconductor technology.

Conclusion

Pin Chia Su's extensive expertise and innovative approach have positioned him as a leading figure in semiconductor advancements. With 22 patents to his name, his contributions continue to influence the landscape of technology, paving the way for future exploration and discoveries in the industry. His work not only reflects his dedication to innovation but also serves as an inspiration for aspiring inventors and engineers worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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