The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Jul. 26, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
National Yang Ming Chiao Tung University, Hsinchu City, TW;
Wei-Xiang You, Kaohsiung City, TW;
Pin Su, Hsinchu County, TW;
Kai-Shin Li, Hsinchu County, TW;
Chenming Hu, Oakland, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
NATIONAL YANG MING CHIAO TUNG UNIVERSITY, Hsinchu City, TW;
Abstract
A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.