Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Pin Chia Su

Ching-Hwanq Su

Ying Hsin Lu

Ru-Shang Hsiao

Chi-Cherng Jeng

Ling-Sung Wang

Volume Chien

Chih-Mu Huang

Chih-Kang Chao

Li Te Hsu

I-Shan Huang

I-i Cheng

Ming-Long Fan

Pi-Ho Hu

Ching-Te Chuang

Che-Min Lin

Ru-shang Hsiao

Yin-Nien Chen

Chien-Yu Hsieh

Chenming Hu

Yi-Wei Chiu

Samuel C Pan

Ching-Chung Su

Wei-Ming You

Fang-Cheng Chen

Po-Zen Chen

Kuo-Hsiu Wei

Chih-Cherng Jeng

Yu-Sheng Su

Chia-Tsung Tso

Tai-Yung Yu

Chiang Jen Peng

Wei-Xiang You

Mei-Jen Wu

Ruey-Yong Deng

Yih Song Chiu

Jiunn-Nan Lin

Tzu Chan Weng

Yu-Peng Lin

Sheng-Chien Tung

Jin Lin Liang

Shih Cheng Yeh

Jiun-Hong Lai

I Cheng Tseng

Hsu Chiung Wen

Yin Shen Chu

Ching-Te (Kent) Chuang

Le Der Shiu

Kai-Shin Li

Chia Lun Chen

Tsung Chuan Chen

A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

Metal gate structures and methods of fabricating the same in field-effect transistors

The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

Circuit structure with gate configuration

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Gate electrode having a work-function layer including materials with different average grain sizes

A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Memory circuit and manufacturing method thereof

Methods of manufacturing a gate electrode having metal layers with different average grain sizes

A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Backside illumination image sensor chips and methods for forming the same

A circuit includes a hybrid switch, which includes a Tunnel Field-Effect Transistor (TFET) having a first source, a first drain, and a first gate. The hybrid switch further includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected to the TFET in parallel, with the MOSFET including a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate.

Hybrid TFET-MOSFET circuit design

A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.

Methods of manufacturing and using a photodiode with concave reflector

Photodiode with concave reflector

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Shanhua, Taiwan

Pin Chia Su