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San Jose, CA, United States of America

Philip D Costello

This inventor holds 18 USPTO granted patents, plus 2 CIPO patents, primarily in Programmable Logic Devices. Top assignee: Xilinx, Inc.. Active years: 1998-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Philip D Costello. Retrieved from https://idiyas.com/inventor/philip-d-costello

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18

% Patents Active = 88.9


Average Co-Inventor Count = 3.5

ph-index = 12

Forward Citations = 452(Granted Patents)


Location History:

  • San Jose, CA (US) (1998 - 2007)
  • Saratoga, CA (US) (2004 - 2016)

Company Filing History:

goldMedal18 out of 5,116 
 
Xilinx, Inc.
 patents

Years Active: 1998-2016

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Areas of Expertise:
Interconnect Multiplexers
Power Reduction
Negative Bias Simulation
Data Monitoring
Programmable Logic Block
High Speed Transceiver
Voltage Regulation
Single Event Upset
Clock Management
Memory Cell
Field Programmable Gate Array
Bus Structure
18 patents (USPTO):Explore Patents
1. 9509307 - Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer (2016-11-29),
2. 7653891 - Method of reducing power of a circuit (2010-01-26),
3. 7600204 - Method for simulation of negative bias and temperature instability (2009-10-06),
4. 7518394 - Process monitor vehicle (2009-04-14),
5. 7283409 - Data monitoring for single event upset in a programmable logic device (2007-10-16),
6. 7265576 - Programmable lookup table with dual input and output terminals in RAM mode (2007-09-04),
7. 7256612 - Programmable logic block providing carry chain with programmable initialization values (2007-08-14),
8. 7215138 - Programmable lookup table with dual input and output terminals in shift register mode (2007-05-08),
9. 7187709 - High speed configurable transceiver architecture (2007-03-06),
10. 7119570 - Method of measuring performance of a semiconductor device and circuit for the same (2006-10-10),
11. 7109783 - Method and apparatus for voltage regulation within an integrated circuit (2006-09-19),
12. 7109746 - Data monitoring for single event upset in a programmable logic device (2006-09-19),
13. 7075333 - Programmable circuit optionally configurable as a lookup table or a wide multiplexer (2006-07-11),
14. 6911842 - Low jitter clock for a physical media access sublayer on a field programmable gate array (2005-06-28),
15. 6822894 - Single event upset in SRAM cells in FPGAs with leaky gate transistors (2004-11-23),

Title: The Innovative Journey of Philip D Costello

Introduction: Philip D Costello, a pioneering inventor based in San Jose, CA, has made significant contributions to the field of technology through his groundbreaking inventions and patents.

Latest Patents: Philip D Costello holds several patents in various technological domains, including artificial intelligence, renewable energy, and telecommunications. His most recent patent involves a cutting-edge algorithm for optimizing solar panel efficiency.

Career Highlights: With a career spanning over two decades, Philip D Costello has worked for leading tech companies in Silicon Valley, where he honed his skills in innovation and problem-solving. He has a proven track record of turning novel ideas into successful products that have revolutionized the industry.

Collaborations: Throughout his career, Philip D Costello has collaborated with top engineers, scientists, and researchers to bring his inventions to life. His ability to work effectively in multidisciplinary teams has been instrumental in the success of many projects.

Conclusion: Philip D Costello's relentless pursuit of innovation and his passion for creating technology that makes a difference have solidified his reputation as a visionary inventor in the tech community. His work continues to inspire future generations of inventors to push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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