The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Jun. 14, 2005
Venu M. Kondapalli, Sunnyvale, CA (US);
Trevor J. Bauer, Boulder, CO (US);
Manoj Chirania, Palo Alto, CA (US);
Philip D. Costello, Saratoga, CA (US);
Steven P. Young, Boulder, CO (US);
Venu M. Kondapalli, Sunnyvale, CA (US);
Trevor J. Bauer, Boulder, CO (US);
Manoj Chirania, Palo Alto, CA (US);
Philip D. Costello, Saratoga, CA (US);
Steven P. Young, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N−1))×2 RAM) having fewer than N (e.g., N−1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N−1)-bit shift register or two 2**(N−2)-bit shift registers.