The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2016
Filed:
Sep. 22, 2014
Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer
Xilinx, Inc., San Jose, CA (US);
Vikram Santurkar, Bengaluru, IN;
Anil Kumar Kandala, Hyderabad, IN;
Santosh Yachareni, Hyderabad, IN;
Shidong Zhou, Milpitas, CA (US);
Robert Fu, Saratoga, CA (US);
Philip Costello, Saratoga, CA (US);
Sandeep Vundavalli, Secunderabad, IN;
Steven P. Young, Boulder, CO (US);
Brian C. Gaide, Erie, CO (US);
XILINX, INC., San Jose, CA (US);
Abstract
An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.