The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Apr. 30, 2004
Manoj Chirania, Palo Alto, CA (US);
Venu M. Kondapalli, Sunnyvale, CA (US);
Martin L. Voogel, Los Altos, CA (US);
Philip Costello, Saratoga, CA (US);
Manoj Chirania, Palo Alto, CA (US);
Venu M. Kondapalli, Sunnyvale, CA (US);
Martin L. Voogel, Los Altos, CA (US);
Philip Costello, Saratoga, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.